In a TDMA communication system, a number of transmitters can transmit on the same frequency channel, but at different times. A remote receiver for receiving a particular transmitted signal knows beforehand at what time the transmitted signal will occur and is enabled only during that time. The use of TDMA makes very efficient use of the frequency spectrum since multiple users may use the same frequency channel at the same time without interfering with one another. FIG. 1 illustrates one type of TDMA system where a plurality of wireless telephones 10, 11, 12, and 13 share a same frequency channel while transmitting to and receiving from a high power transponder base cell 14. All communications between telephones 10-13 are routed through base cell 14. Such a TDMA system may be the Personal Handy Phone System whose requirements are described in the RCR Standard-28, incorporated herein by reference. As an alternate embodiment, such a TDMA system may be the ETSI DECT standard, also incorporated herein by reference. Further, slow frequency hopping systems, compliant with CFR Title 47, part 15, and intended for the U.S. ISM-bands, may be derived from the aforementioned formal standards.
In a TDMA system, each remote transceiver, when active, is allocated certain time slots within which it may transmit a bursted signal or receive a bursted signal. FIG. 2 illustrates a frame 16 containing slots 0 through 7, where frame 16 is repeated on a single frequency channel. The period of frame 16 may be, for example, 5 milliseconds. Assuming all four wireless telephones 10-13 in FIG. 1 are being actively used at the same time, telephones 10, 11, 12, and 13 may be allocated slots 0, 1, 2, and 3, respectively, for transmitting bursted signals to base cell 14, while telephones 10, 11, 12, and 13 may be allocated slots 4, 5, 6, and 7, respectively, for receiving bursted signals from base cell 14. The amount of information stored in each of telephones 10-13 during a frame period is transmitted in a burst within a single slot.
A sample protocol 18 for a slot is also shown in FIG. 2, where protocol 18 dictates the information required to be transmitted during a single slot. Protocol 18 may consist of a ramp-up field 20, a start symbol field 21, a clock recovery field 22, a slot sync (or Unique Word) field 23, a data field 24, a CRC field (for error correction and verification), and a guard band field 26. The lengths and types of fields in a protocol vary depending on the mode of the transceiver (e.g., set up mode, transmit/receive mode, etc.) While in the traffic mode, where voice is to be transmitted, data field 24 contains audio data. Data field 24 is referred to as the traffic channel or TCH.
In one embodiment, the bit rate of the transmitted bits in a frame 16 is approximately 384K bits per second, and the corresponding symbol rate is, therefore, 192K symbols per second.
FIG. 3 is a basic illustration of one type of TDMA communication system. ROM 34 contains certain program instructions for a microprocessor 36 connected to a system bus 38. RAM 40 is used for storing information for various purposes, such as storing program variables, mailbox information, and stack parameters.
The portion of the TDMA system which creates the various slots and controls the timing of the information within each of the slots is the burst mode controller (BMC) 42. Generally, the BMC 42 consists of a BMC bus controller 44, a voice coder 46 for generating PCM audio data for the data field in a slot, a data RAM 48 containing certain data and protocol bits to be inserted into a slot, and a sequencer 50 which controls the overall bit synchronization of a slot as well as controls the activation of the various modulator interface modules 51 which either sink or source the bits within a slot. Also shown is a block 52 designating other devices unrelated to an understanding of the invention, which would be conventional and understood by those skilled in the art.
A peripheral bus interface unit 56 is also connected to system bus 38 and controls access to the peripheral bus 57, to which is connected various input/output devices 58 and other interfacing devices 59 necessary for telephones 10-13 to transmit RF signals and receive RF signals.
FIG. 4 illustrates the pertinent portions of a conventional sequencer 50. Sequencer 50 includes a core 60 whose output is a multi-bit control signal which controls various devices and operations in the TDMA system to generate bits for transmission in a slot at the proper bit times. By selectively enabling and disabling the devices and operations at the proper times, the correct protocols for a slot are generated, as shown in FIG. 2, along with the synchronized insertion of data and CRC bits. The particular sequencer 50 routine carried out is determined by the addressed instructions in a microcode memory 62. For example, a first type of protocol would be created by sequencer 50 during a set-up mode, and a different protocol would be set up for a voice communication (traffic mode).
Sequencer 50 uses a microcode RAM 62 containing a main program 64 along with various subroutines, such as a transmit subroutine 66 and a receive subroutine 68, although many other sub-routines may also exist as would be understood by those skilled in the art. A bit rate oscillator 70, whose bit rate and phase have been adjusted to be synchronized with the base cell 14 (FIG. 1) bit rate, controls the timing of core 60 so that the control code outputs are synchronized with the required slot timing.
The main program 64 is a sequential program typically containing no conditions. The microprocessor 36 (FIG. 3) needs to insert a jump command at the proper time into the main program 64 in order for the microcode to jump to a particular subroutine, such as transmit or receive.
Additionally, the microcode in sequencer 50 is developed for a standard use of the TDMA system. However, certain TDMA systems may require different protocols or slightly different sequences. For these specialized protocols, the microprocessor 36 in FIG. 3 must then transfer the appropriate instructions from ROM 34 into the microcode RAM 62 at the proper times to create the custom protocols.
Microcode RAM is much larger than microcode ROM and takes up considerable silicon real estate. Additionally, the interaction of the microprocessor 36 with the sequencer microcode creates complex timing considerations. This conventional type of sequencer 50 is also limited in other respects.
Further, while attempting to obtain and maintain synchronization of the frame and slots, the system is susceptible to synchronizing on a false slot synchronization code when the synchronization code is duplicated by coincidence by noise or data. Such falsing rates in an AWGN channel are a consequence of the bit rate, the number of errors to be allowed, and the length of the Unique Word field to be correlated against. These falsing rates are specified by the binomial theorem.
What is needed is a more flexible sequencer whose microcode does not need to be reprogrammed by a microprocessor. What is also needed is a TDMA system which is less susceptible to false synchronization codes.